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| Semiconductor April 1999 CT UCT ODU E PR E PROD ) ET A OL UT OBS UBSTIT HI-0509( E S 509A, G SIBL POS G409, D D IH6208 8-Channel CMOS Analog Multiplexer Features * Ultra Low Leakage - ID(OFF) 100pA (Typ) * rDS(ON) < 400 Over Full Signal and Temperature Range * Power Supply Quiescent Current Less Than 100A * 14V Analog Signal Range * No SCR Latchup * Break-Before-Make Switching * Binary Address Control (2 Address Inputs Control 2 Out of 8 Channels) * TTL and CMOS Compatible Address Control * Pin Compatible with DG509A, HI-509 and ADG509A * Internal Diode in Series with V+ for Fault Protection Description The IH6208 is a CMOS 2 of 8 multiplexer. The part is a plug-in replacement for the DG509A. Two-line binary decoding is used so that the 8 channels can be controlled in pairs by the binary inputs; additionally a third input is provided for use as a system enable. When the ENABLE input is high (5V), the channels are sequenced by the 2 line binary inputs, and when low (0V) all channels are off. The 2 Address inputs arecontrolled by TTL logic or CMOS logic elements with a "0" corresponding to any voltage less than 0.8V and a "1" corresponding to any voltage greater than 2.4V. Note that the ENABLE input must be taken to 5V to enable the system, and less than 0.8V to disable the system. Part Number Information PART NUMBER IH6208MJE IH6208MJE/883B IH6208MFE/883B IH6208CJE IH6208CPE TEMP. RANGE (oC) -55 to 125 -55 to 125 -55 to 125 0 to 70 0 to 70 PACKAGE 16 Ld CERDIP 16 Ld CERDIP 16 Ld Flat Pack 16 Ld CERDIP 16 Ld PDIP PKG. NO. F16.3 F16.3 K16.A F16.3 E16.3 Pinout IH6208 (CERDIP, PDIP) TOP VIEW A0 1 EN 2 V- 3 S1a 4 S2a 5 S3a 6 S4a 7 Da 8 16 A1 15 GND 14 V+ 13 S1b 12 S2b 11 S3b 10 S4b 9 Db Functional Diagram S1a S2a S3a S4a S1b S2b S3b S4b A0 A1 EN 2 LINE BINARY ADDRESS INPUTS (0 0) AND EN = 5V (EN = "1" for +5V, "0" for 0V) ABOVE EXAMPLE SHOWS CHANNELS 1a AND 1b ON. Da Db ADDRESS DECODER 1 OF 4 ENABLE INPUT TRUTH TABLE A1 x 0 0 1 1 A0 x 0 1 0 1 EN 0 1 1 1 1 ON SWITCH PAIR None 1a, 1b 2a, 2b 3a, 3b 4a, 4b NOTE: A0 , A1 Logic "1" = VAH 2.4V, VENH 4.5V Logic "0" = VAL 0.8V. CAUTION: These devices are sensitive to electrostatic discharge. Users should follow proper IC Handling Procedures. Copyright (c) Harris Corporation 1997 File Number 3157.2 12-129 IH6208 Absolute Maximum Ratings VIN (A, EN) to Ground . . . . . . . . . . . . . . . . . . . . . . . . . . -15V to 15V VS or VD to V+ . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .0V, -36V VS to VD to V- . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 0V, 36V V+ to Ground . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18V V- to Ground . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .-18V Current (Any Terminal) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30mA Current (Analog Source or Drain) . . . . . . . . . . . . . . . . . . . . . . 20mA Thermal Information Thermal Resistance (Typical, Note 1) JA (oC/W) JC (oC/W) CERDIP Package . . . . . . . . . . . . . . . . 80 22 Ceramic Flatpack Package . . . . . . . . . 85 25 PDIP Package . . . . . . . . . . . . . . . . . . . 100 N/A Maximum Junction Temperature (Hermetic Package) . . . . . . . . 175oC Maximum Junction Temperature (Plastic Package) . . . . . . . . 150oC Maximum Storage Temperature Range . . . . . . . . . .-65oC to 150oC Maximum Lead Temperature (Soldering 10s) . . . . . . . . . . . . . 300oC Operating Conditions Temperature Range C Suffix . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .0oC to 70oC M Suffix . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . -55oC to 125oC CAUTION: Stresses above those listed in "Absolute Maximum Ratings" may cause permanent damage to the device. This is a stress only rating and operation of the device at these or any other conditions above those indicated in the operational sections of this specification is not implied. NOTE: 1. JA is measured with the component mounted on an evaluation PC board in free air. Electrical Specifications V+ = 15V, V- = -15V, VEN = +5V, Ground = 0V, Unless Otherwise Specified, (Note 4) NO TESTS PER TEMP M SUFFIX (oC) TYP 25oC C SUFFIX (oC) PARAMETER SWITCH rDS(ON) MEASURED TERMINAL TEST CONDITIONS -55 25 125 0 25 70 UNITS S to D 8 180 VD = +10V, IS = -1.0mA Sequence Each Switch On VAL = 0.8V, VAH = 2.4V VD = -10V, IS = -1.0mA Sequence Each Switch On VAL = 0.8V, VAH = 2.4V rDS(ON) = rDS ( ON ) MAX -rDS ( ON ) M I N -----------------------------------------------------------------------------------, rDS ( ON ) AV G VS = 10V 300 300 400 350 350 450 8 150 300 300 400 350 350 450 rDS(ON) 20 - - - - - - % IS(OFF) S 8 8 0.002 0.002 0.03 0.03 0.1 VS = 10V, VD = -10V VS = -10V, VD = 10V, VEN = 0.8V VD = 10V, VS = -10V, VEN = 0.8V VD = -10V, VS = 10V, VEN = 0.8V VS(ALL) = VD = 10V, Sequence Each Switch On VAL = 0.8V, VAH = 2.4V VS(ALL) = -10V, Sequence Each Switch On VAL = 0.8V, VAH = 2.4V - 0.5 0.5 2 2 2 50 50 50 50 50 - 1 1 5 5 5 50 50 100 100 100 nA nA nA nA nA ID(OFF) D 2 2 ID(ON) D 8 8 0.1 - 2 50 - 5 100 nA INPUT IAN(ON) IAN(OFF) IA A0 , A1 EN A0 , A1 2 2 2 1 0.01 0.01 0.01 0.01 VA = 0V VA = 14V VEN = 5V, All VA = 0V (Address Pins) VEN = 0V, All VA = 0V (Address Pins) -10 10 -10 -10 -30 30 -30 -30 -10 10 -10 -10 -30 30 -30 -30 A A A A 12-130 IH6208 Electrical Specifications V+ = 15V, V- = -15V, VEN = +5V, Ground = 0V, Unless Otherwise Specified, (Note 4) (Continued) NO TESTS PER TEMP M SUFFIX (oC) TYP 25oC C SUFFIX (oC) PARAMETER DYNAMIC tTRANSITION tOPEN tEN(ON) tEN(OFF) "OFF" Isolation MEASURED TERMINAL TEST CONDITIONS -55 25 125 0 25 70 UNITS D D D D D 0.3 0.2 0.6 0.4 60 See Figure 1 See Figure 2 See Figure 3 See Figure 3 VEN = 0V, RL = 200, CL = 3pF, VS = 3VRMS , f = 500kHz VS = 0V, VEN = 0V, f = 140kHz to 1MHz VD = 0V, VEN = 0V, f = 140kHz to 1MHz VS = 0V, VD = 0V, VEN = 0V, f = 140kHz to 1MHz - 1 1.5 1 - - - - - s s s s dB CS(OFF) CD(OFF) CDS(OFF) S D D to S 5 12 1 - - - - - - pF pF pF SUPPLY Positive Supply Current Negative Supply Current Positive Standby Current Negative Standby Current NOTE: 2. See "Enable Input Strobing Levels" in Application Section. V+ VV+ V1 1 1 1 40 2 1 1 VEN = 5V, All VA = 0V or 5V VEN = 5V, All VA = 0V or 5V VEN = 0V, All VA = 0V or 5V VEN = 0V, All VA = 0V or 5V 200 100 100 100 1000 1000 1000 1000 A A A A Switching Information +15V D1 S1a S2a S IH6208 3a S4a S1b A1 S2b A0 S3b S4b EN GND +5V -15V VD2 RP CP PROBE IMPEDANCE RP 1M CP 30pF VOUT V+ 3.0V 1.4V 0.8V 0 10V VS1b 0.9VS1b 0 PROBE 0.9VS4b VS4b S1b(ON) VA 50 10V ttrans S4b(ON) ttrans FIGURE 1. tTRANSITION SWITCHING TEST CIRCUIT AND WAVEFORMS 12-131 IH6208 Switching Information S1b S2b A1 THRU A0 IH6208S3b S4b EN D2 200 GND -15V (Continued) +15V -2V SWITCH OUTPUT VOUT (SEE PINOUT) VOUT 35pF VA +0.8V +3V 50% tOPEN tOPEN VA +5V 0 0.9VO VO VS FIGURE 2. tOPEN (BREAK-BEFORE-MAKE) SWITCHING TEST CIRCUIT AND WAVEFORMS +15V S1b ALL OTHERS IH6208 EN VEN GND S4b D2 200 -15V VOUT 35pF -5V VEN tr and tf 100ns +0.8V 0V 0.1VO SWITCH OUTPUT VOUT (SEE FIGURE 1) 0.9VO VO -5V +5V 50% tEN(ON) tEN(OFF) A1 A0 FIGURE 3. tON AND tOFF SWITCHING TEST CIRCUIT AND WAVEFORMS IH6208 Application Information ENABLE Input Strobing Levels The ENABLE input on the IH6208 requires a minimum of +4.5V to trigger to the "1" state and a maximum of +0.8V to trigger to the "0" state. If the ENABLE input is being driven from TTL logic, a pull-up resistor of 1k to 3k is required from the gate output to +5V supply. (See Figure 4) When the EN in put is driven from CMOS logic, no pullup is necessary, see Figure 5. The supply voltage of the CD4009 affects the switching speed of the IH6208; the same is true for TTL supply voltage levels. The following chart shows the effect, on ttrans for a supply varying from +4.5V to +5.5V. CMOS OR TTL SUPPLY VOLTAGE TYPICAL TTRANS AT 25oC Using the IH6208 with Supplies Other Than 15V The IH6208 can be used with power supplies ranging from 6V to 16V. The switch rDS(ON) will increase as the supply voltages decrease, however, the multiplexer error term (the product of leakage times rDS(ON)) will remain approximately constant since leakage decreases as the supply voltages are reduced. Caution must be taken to ensure that the enable (EN) voltage is at least 0.7V below V+ at all times. If this is not done, the Address input strobing levels will not function properly. This may be achieved quite simply by connecting EN (pin 2) to V+ (pin 14) via a silicon diode as shown in Figure 6. When using this type of configuration, a further requirement must be met: the strobe levels of A0 and A1 must be within 2.5V of the EN voltage in order to define a binary "1" state. For the case shown in Figure 6 the EN voltage is 11.3V which means that logic high at A0 and A1 is +8.8V (logic low continues to be 0.8V). In this configuration the IH6208 cannot be driven by TTL (+5V) or CMOS (+5V) logic. It can be driven by TTL open collector logic or CMOS logic with +12V supplies. If the logic and the IH6208 have common supplies, the EN pin should again be connected to the supply through a silicon diode. In this case, tying EN to the logic supply directly will not work since it violates the 0.7V differential voltage required between V+ and EN, (See Figure 7). A 1F capacitor can be placed across the diode to minimize switching glitches. +4.5V +4.75V +5.00V +5.25V +5.50V 400ns 300ns 250ns 200ns 175ns The throughput rate can therefore be maximized by using a +5V to +5.5V supply for the ENABLE Strobe Logic. The examples shown in Figure 4 and 5 deal with ENABLE strobing when expansion to more than eight channels is required. In these cases the EN terminal acts as a fourth address input. If eight channels or less are being multiplexed, the EN terminal can be directly connected to +5V logic supply to enable the IH6208 at all times. 12-132 IH6208 Switching Information 1 2 3 4 5 6 7 DM7404N TTL LOGIC 14 13 12 11 10 9 8 +3V 0V +5V 1k A0 1 EN 2 16 A1 15 14 +15V IH6208 13 S1b 12 S2b 11 S3b 10 S4b 9 D2 -15V 3 S1a 4 S2a 5 S3a 6 S4a 7 D1 8 FIGURE 4. ENABLE INPUT STROBING FROM TTL LOGIC +5V 1 2 3 16 15 14 CD4009 4 CMOS LOGIC 13 5 6 7 8 12 11 10 9 A0 1 EN 2 16 A1 15 14 +15V IH6208 13 S1b 12 S2b 11 S3b 10 S4b 9 D2 -15V 3 S1a 4 S2a 5 S3a 6 S4a 7 D1 8 FIGURE 5. CMOS LOGIC DRIVING ENABLE PIN 1N914 A0 1 EN 2 16 A1 15 14 IH6208 13 12 11 10 9 D2 = B CHANNEL DRAIN OUTPUT (COMMON) B CHANNEL SOURCE INPUTS +12V -12V 3 4 5 A CHANNEL SOURCE INPUTS 6 7 A CHANNELS COMMON DRAIN OUTPUT = D1 8 FIGURE 6. IH6208 CONNECTION DIAGRAM FOR LESS THAN 15V SUPPLY OPERATION 12-133 IH6208 Switching Information (Continued) 1N914 A0 1 2 3 4 5 6 7 8 CD4009A 16 15 14 13 12 11 10 9 EN 1 2 16 15 14 IH6208 A1 -12V 3 S1a 4 S2a 5 S3a 6 S4a 7 D1 8 +12V 13 S1b 12 S2b 11 S3b 10 S4b 9 D2 FIGURE 7. IH6208 CONNECTION DIAGRAM WITH ENABLE INPUT STROBING FOR LESS THAN 15V SUPPLY OPERATION Peak-to-Peak Signal Handling Capability The IH6208 can handle input signals up to 14V (actually -15V to +14.3V because of the input protection diode) when using the 15V supplies. The electrical specifications of the IH6208 are guaranteed for 10V signals, but the specifications have very minor changes for 14V signals. The notable changes are slightly lower rDS(ON) and slightly higher leakages. Schematic Diagram S1X S2X S3X S4X 1) A0' OR A0' 2) A1' OR A1' 1 2 ADDRESS DECODER V- S4X V- DX EN EN INPUT EN' AND LEVEL SHIFTER GND V- AX ADDRESS INPUT GND VV++ LEVEL SHIFTER V- AX' AX' V+ VGND FIGURE 8. 1/ 2 IH6208 SCHEMATIC DIAGRAM 12-134 IH6208 V++ P EN P P P N P N N N N EN' GND V- FIGURE 9. ENABLE INPUT AND LEVEL SHIFTER V++ P AX N P AX' P EN V++ P GND N N N VAX' FIGURE 10. ADDRESS INPUT AND LEVEL SHIFTER 12-135 |
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